During this test, QuickTech Self Boot tests all registers and status ports of the two DMA controllers. The DMA controller is very critical to a system’s operation because it contains separate channels that allow I/O devices to have direct access to the system’s RAM for high speed data transfers without using the microprocessor. Once programmed, the DMA controller can signal the processor to leave the bus temporarily so that it may complete the actual data transfer by itself at high speeds. The DMA controller can actually address and transfer a maximum of 64k bytes at a time, so additional circuitry is added in the system design to accommodate the extra address lines needed to access the system’s entire memory.
DMA Controller 1 contains Channels 0 – 3. Channel 0 is a spare; Channel 1 is reserved for networks; Channel 2 is used by the disk controller, and Channel 3 is spare. DMA controller 2 contains Channels 4 – 7. Channel 4 is used to cascade channels 0 – 3 of DMA controller 1. Each DMA controller has a 6-bit mode word and four 16-bit registers. All of these registers are fully tested with the QuickTech Self Boot .
